In high-speed digital communication with a data transmission speed of 1 [Gb/s] or more for transmitting time division multiplexed data and receiving the transmitted data with time separation (demultiplexing), a receiver is in need of a clock corresponding to the transmission rate for discrimination and time separation of received data. Since clock components are extracted from high-speed data prior to time separation and the clocks thus extracted are used for discrimination and time separation, a clock extraction circuit operating at a high speed is required, which greatly depends on device characteristics. If the data transfer speed exceeds 1 Gb/s, for example, a high-speed phase comparator can hardly be realized.
FIG. 12 shows a block diagram showing the structure of a conventional clock extraction circuit. In this figure, the conventional clock extraction circuit includes an edge detection circuit 1 detecting a point of transition of a non-return-to-zero (NRZ) signal entered at an input terminal 11, and a phase comparator 3 for phase comparison between the NRZ signal received and an output signal of a voltage controlled oscillator (VCO) 6 by receiving the output of the edge detection circuit 1 at its one input terminal and the output of the VCO 6 at its other terminal. The conventional clock extraction circuit also includes a low-pass filter 5 for outputting only pre-set low frequency range signals of an output of the phase comparator 3, and VCO 6 oscillating pulse signals depending on an output signal (signal voltage) outputted by the low-pass filter 5 for outputting pulse signals to an output terminal 12 and to the other input terminal of the phase comparator 3.